The approximately equal strength of PMOS and NMOS devices seen on newer processes is a result of strained silicon, which was introduced on planar processes. The amount of strain in the first generation of strained silicon wasn't sufficient to achieve equal mobility but it did reduce the mobility gap between PMOS and NMOS devices. With increasing strain in newer process iterations, after 3 or 4 generations PMOS mobility exceeded NMOS, delivering the results that you noted. This aligned in time with the FINFET transition. This differential impact occurs because it is easier to deliver large amounts of compression (benefiting hole mobility) to PMOS devices than to deliver similar amounts of tension (benefiting electron mobility) to NMOS devices.
I was aware that strain was first used with planar but assumed it was avoidable in SRAM regions (perhaps it is in some FinFET) but the literature becomes concerned about single fins and balance mostly in the FinFET generations. I was not aware PFET actually got stronger than N! That would imply it is better to build SRAM cells upside down using PFET for access transistors and NFET for the passive side of the inverters. The size would not change just mirror all the layout.
Next post discusses reducing the PFET strain for various reasons.
I recall someone building an experimental "upside down" SRAM, but don't remember the results.
CFETs are an interesting question. I expect that strain will still be available. It's just too valuable to give up entirely, and modern (uniaxial) strain engineering is done in the plane of the devices.
Hi Shakanth, thanks for asking. As I explained in some of the early posts I had used OpenRoad tools which include KLayout but did not find the 2D layouts very helpful, as I am partially colorblind. And I was really curious to get into details of placement and cell design, so I decided to implement the rules manually (which is why I say they are "mock" rules, not likely to work without proper design rules checking and adjustments).
I am fairly adept with SketchUp (from Trimble) which was used a lot for physical design of computers and racks, so it is what I used. I cannot say it is ideal, but it is productive and fairly easy to use while keeping track of the placement rules. I also tried using Blender (which is free, and astounding and probably much better with large scale design) but found the UI of Blender has a lot of options that distract from what I want, and managing the viewport was overly complicated for abstract geometry. So I just ended up back using SketchUp. Its optimizations for inferring physical placements, intended for architects designing buildings or landscapes, actually do a useful job of keeping the circuit elements aligned.
I have considered making a tool to use geometry exported from Sketchup to create a layers file for use in KLayout but it is not high on my priority list. It would be nice to have a bridge back into real EDA tools.
If you know of other 3D geometry programs with a productive UX, let me know!
The slowdown of SRAM scaling is mostly because it is a single cell design which was optimized years ago. Logic can scale denser not just because of fin pitch and contact pitch but also because of wiring improvements and reduction in fin count. SRAM has only fin pitch and contact pitch, because it needs no extra levels of wiring and it collapsed to a single fin almost as soon as FinFET was developed.
Meanwhile, of those two remaining dimensions, CPP (the contact poly pitch, distance between source and drain polySi contacts) is pretty much stopped by the minimum effective length of a transistor channel. SRAM cannot cut that too short or it will leak, so it probably cannot have a channel shorter than 20nm. Ribbons can get shorter, about 16nm IIUC, because they finish controlling all 4 sides of the channel. So there should be a small step improvement in ribbon FETs, if no steps backward occur in other contributions to CPP. Even better control is reported in novel materials like WS2 or MoS2 2D films, which might shorten the channel a few more nm, if construction problems can be made practical.
The sideways distance between fins (or ribbons) might get significantly smaller. The SRAM layout requires space for split gates and contacts and compatibility with logic - which means sharing lithographic masks and illumination - tends to keep the fin distance about the same as every second fin of the logic, which is also the distance at which techniques for split control and contact are reliably developed. However, there is no physical reason why that should not get narrower if the lithography gets better. You could probably almost halve the sideways spacing before running into material limits on dielectric thickness, though the fins themselves will not get thinner. Maybe a 30% potential there with better lithography and processing, but no physical material limits (the CPP is already at material limits)? Expensive machines and precise work needed to get there. Not much in the literature suggesting this is happening though, so maybe I am missing some obvious other problem to narrower fin spacing. In logic it has serious drawbacks with capacitive coupling, but for SRAM those should not be show-stopping in the same way.
CFET is also predicted to improve density by maybe 50% by stacking complementary N and P channels above each other. It does not work out to be doubling since the channels are not everything, there are wires and contacts in the vertical structure which also take up horzontal space. Very early days on that, I think CFET is currently a 2028 roadmap item.
It appears industry is planning to move towards chiplets and move SRAM or at least L3 cache to slightly older nodes. There is a plenty of room left to improve hybrid bonding technology.
Remains to be seen if MRAM / FRAM or any other new memory can take over the role of dense on chip memory in future.
When an RF guy like me looks at internal workings of digital memory, I am constantly reminded how much expertise is needed to make the electronics we do! I’m going to try and understand this one. Thanks!
The approximately equal strength of PMOS and NMOS devices seen on newer processes is a result of strained silicon, which was introduced on planar processes. The amount of strain in the first generation of strained silicon wasn't sufficient to achieve equal mobility but it did reduce the mobility gap between PMOS and NMOS devices. With increasing strain in newer process iterations, after 3 or 4 generations PMOS mobility exceeded NMOS, delivering the results that you noted. This aligned in time with the FINFET transition. This differential impact occurs because it is easier to deliver large amounts of compression (benefiting hole mobility) to PMOS devices than to deliver similar amounts of tension (benefiting electron mobility) to NMOS devices.
Thank you for the additional info!
I was aware that strain was first used with planar but assumed it was avoidable in SRAM regions (perhaps it is in some FinFET) but the literature becomes concerned about single fins and balance mostly in the FinFET generations. I was not aware PFET actually got stronger than N! That would imply it is better to build SRAM cells upside down using PFET for access transistors and NFET for the passive side of the inverters. The size would not change just mirror all the layout.
Next post discusses reducing the PFET strain for various reasons.
I have wondered if we will lose strain in CFETs?
I recall someone building an experimental "upside down" SRAM, but don't remember the results.
CFETs are an interesting question. I expect that strain will still be available. It's just too valuable to give up entirely, and modern (uniaxial) strain engineering is done in the plane of the devices.
Hello, what application did you use to generate those layouts and view them in 3d?
Hi Shakanth, thanks for asking. As I explained in some of the early posts I had used OpenRoad tools which include KLayout but did not find the 2D layouts very helpful, as I am partially colorblind. And I was really curious to get into details of placement and cell design, so I decided to implement the rules manually (which is why I say they are "mock" rules, not likely to work without proper design rules checking and adjustments).
I am fairly adept with SketchUp (from Trimble) which was used a lot for physical design of computers and racks, so it is what I used. I cannot say it is ideal, but it is productive and fairly easy to use while keeping track of the placement rules. I also tried using Blender (which is free, and astounding and probably much better with large scale design) but found the UI of Blender has a lot of options that distract from what I want, and managing the viewport was overly complicated for abstract geometry. So I just ended up back using SketchUp. Its optimizations for inferring physical placements, intended for architects designing buildings or landscapes, actually do a useful job of keeping the circuit elements aligned.
I have considered making a tool to use geometry exported from Sketchup to create a layers file for use in KLayout but it is not high on my priority list. It would be nice to have a bridge back into real EDA tools.
If you know of other 3D geometry programs with a productive UX, let me know!
Would love to hear your thoughts on the impact of end of SRAM scaling … and if any other technology can replace it ?
The slowdown of SRAM scaling is mostly because it is a single cell design which was optimized years ago. Logic can scale denser not just because of fin pitch and contact pitch but also because of wiring improvements and reduction in fin count. SRAM has only fin pitch and contact pitch, because it needs no extra levels of wiring and it collapsed to a single fin almost as soon as FinFET was developed.
Meanwhile, of those two remaining dimensions, CPP (the contact poly pitch, distance between source and drain polySi contacts) is pretty much stopped by the minimum effective length of a transistor channel. SRAM cannot cut that too short or it will leak, so it probably cannot have a channel shorter than 20nm. Ribbons can get shorter, about 16nm IIUC, because they finish controlling all 4 sides of the channel. So there should be a small step improvement in ribbon FETs, if no steps backward occur in other contributions to CPP. Even better control is reported in novel materials like WS2 or MoS2 2D films, which might shorten the channel a few more nm, if construction problems can be made practical.
The sideways distance between fins (or ribbons) might get significantly smaller. The SRAM layout requires space for split gates and contacts and compatibility with logic - which means sharing lithographic masks and illumination - tends to keep the fin distance about the same as every second fin of the logic, which is also the distance at which techniques for split control and contact are reliably developed. However, there is no physical reason why that should not get narrower if the lithography gets better. You could probably almost halve the sideways spacing before running into material limits on dielectric thickness, though the fins themselves will not get thinner. Maybe a 30% potential there with better lithography and processing, but no physical material limits (the CPP is already at material limits)? Expensive machines and precise work needed to get there. Not much in the literature suggesting this is happening though, so maybe I am missing some obvious other problem to narrower fin spacing. In logic it has serious drawbacks with capacitive coupling, but for SRAM those should not be show-stopping in the same way.
CFET is also predicted to improve density by maybe 50% by stacking complementary N and P channels above each other. It does not work out to be doubling since the channels are not everything, there are wires and contacts in the vertical structure which also take up horzontal space. Very early days on that, I think CFET is currently a 2028 roadmap item.
Thanks for the detailed explanation.
It appears industry is planning to move towards chiplets and move SRAM or at least L3 cache to slightly older nodes. There is a plenty of room left to improve hybrid bonding technology.
Remains to be seen if MRAM / FRAM or any other new memory can take over the role of dense on chip memory in future.
When an RF guy like me looks at internal workings of digital memory, I am constantly reminded how much expertise is needed to make the electronics we do! I’m going to try and understand this one. Thanks!